The manufacturing of integrated circuits (ICs) requires many process steps which are executed with precision and accuracy. Precision is important in that the ultimate dimensions are becoming smaller and smaller, on order of less than one micron. Accuracy is important in that the related process steps are often repeatable over time within a controlled range.
A significant part of many wafer manufacturing processes involves photolithography. Photolithography involves taking an image of a part of the electronic circuit, rendering this part of the circuit onto a photographic plate, sometimes referred to as a photomask; and using the photomask and a light source to print that image onto a silicon wafer upon which a light-sensitive emulsion, or a photoresist, has been applied. The exposed photoresist is developed to reveal the desired circuit elements.
Other processes and treatments complete the layer for a given part of the electronic circuit. A given electronic circuit may have a number of photolithographic steps. The number of photolithographic steps often increase as circuits become more and more complex.
Two apparatuses used for printing a mask pattern onto a silicon wafer are the "projection aligner" and the "stepper".
FIG. 1a shows an example of a "projection aligner's" view of the alignment structure. In projection aligner printing, typically all of the product die on the wafer are printed simultaneously. For example, if a wafer substrate has the capacity to hold 150 die, the mask will have 150 images on it. The printing is at a 1:1 ratio. In one typical projection aligner system, for example, the optical system includes two reflecting surfaces. The light, typically, supplied by a high energy source (e.g., a mercury lamp), passes through a point on the photomask to a primary mirror. The light bounces off the primary mirror onto a secondary mirror. From the secondary mirror, it again bounces back to the primary mirror. Here the image on the photomask is projected onto the wafer substrate. To assure accurate alignment, the apparatus relies upon receiving a reflected light signature of the wafer substrate's alignment target so that it can be aligned with the photomask's corresponding marks.
One or more of these alignment structures are placed about a silicon wafer substrate to aid in aligning the plurality of photolithography steps used in a typical sub-micron process to manufacture a semiconductor device. Subsequent layers' photomasks have corresponding alignment marks on them which correspond to those marks printed previously on the silicon wafer substrate. Consequently, inter-layer alignment is maintained throughout the building of the semiconductor device.
FIG. 1b shows an application of an example embodiment in a photolithography process which uses "steppers". In using steppers, one pattern of a layer of the semiconductor device is placed on a reticle. The image on the reticle may be about 5 times larger than the final printed image on the wafer. The stepper optics reduce the reticle size image to the final device size. As a wafer is printed, the "stepper" aligns to the previously printed die. The wafer steps along and the aligner prints one die at a time. Each die has at least one of these novel alignment marks to assure alignment throughout the building of the semiconductor device.
Each step builds an additional layer of the circuit upon the previously built ones. To assure that the layers line up with one another, the subsequent layers are printed relative to the first.
Alignment structures are sometimes included with the electronic circuit as part of its set of photomasks. These structures enable the alignment apparatus to reference correctly the current mask plate's image with the previously printed patterns on the wafer substrate. Typically, the alignment apparatus measures the reflected light off the surface topography of the alignment structure of the wafer. This reflected light "signature" enables the instrument to properly reference the subsequent photomask's alignment structure to that on the wafer, thereby permitting proper connections between the circuits.
The trend of printing smaller and smaller geometries has made the process of aligning wafers more difficult. Topographical properties of each layer printed on the wafer substrate provide a reflected light signature for the aligner. The properties of the surface topography which are useful for alignment impose significant limitations on the ability to shrink down the geometries of the semiconductor devices and to build additional layers. Consequently, as the technology approaches the sub-micron range, the process strives to smooth out these topographical properties.